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課程資訊 |
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課程名稱 |
邏輯合成與驗證 LOGIC SYNTHESIS AND VERIFICATION | |
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開課學期 |
98-1 | |
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授課對象 |
電機資訊學院 電子工程學研究所 | |
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授課教師 |
江介宏 | |
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課號 |
EEE5028 | |
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課程識別碼 |
943 U0300 | |
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班次 |
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學分 |
3 | |
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全/半年 |
半年 | |
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必/選修 |
選修 | |
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上課時間 |
星期三6,7,8(13:20~16:20) | |
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上課地點 |
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備註 |
總人數上限：50人 | |
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課程簡介影片 |
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核心能力關聯 |
核心能力與課程規劃關聯圖 | |
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課程大綱
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課程概述 |
Logic synthesis is the one of the important subject in EDA. It bridges the gap between high-level design and physical design. It is mainly concerned about how to automatically and effectively translate register-transfer-level designs into transister-level circuits. Verification, on the other hand, ensures the equivalence between high-level design and low-level implementation.
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課程目標 |
Boolean methods and their applications will be introduced. The topics to be covered include 1) Boolean algebra, 2) Boolean representation and reasoning, 3) two-level logic minimization, 4) multi-level logic minimization, 5) timing analysis and optimization, 6) technology mapping, 7) sequential optimization, 8) verification, and 9) other advanced topics.
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課程要求 |
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預期每週課後學習時數 |
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Office Hours |
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指定閱讀 |
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參考書目 |
TEXTBOOK: NO REQUIRED TEXTBOOK. LECTURE NOTES WILL BE PROVIDED.
REFERENCE: LOGIC SYNTHESIS AND VERIFICATION. S. HASSOUN AND T. SASSO (EDITORS). KLUWER ACADEMIC PUBLISHERS, 2001. LOGIC SYNTHESIS AND VERIFICATION ALGORITHMS. G. HACHTEL AND F. SOMENZI. KLUWER ACADEMIC PUBLISHERS, 1996. BOOLEAN REASONING. F. BROWN. KLUWER ACADEMIC PUBLISHERS, 1990. | |
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評量方式 (僅供參考) |
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課程進度 |
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週次 |
日期 |
單元主題 |
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